Recently, semiconductor devices for portable electronic devices are being required to scale down as the portable electronic devices are getting ever smaller. Accordingly, the trend calls for more efficient packaging process for the semiconductor devices. A package-on-package (POP) process is one such packing process used to stack multiple ones of the semiconductor devices.
FIG. 1A is a cross-sectional view illustrating a conventional semiconductor device. In FIG. 1A, a semiconductor chip 12 is mounted face-down on a substrate 10 as an interconnection substrate through a flip chip connection using a bump 14. The semiconductor chip 12 is affixed to the substrate 10 with an underfill resin 16. The semiconductor chip 12 is sealed with a resin molding portion 18. Land electrodes 20 formed at the periphery of the semiconductor chip 12 are used to electrically couple the semiconductor device of FIG. 1 with another semiconductor device. Solder balls 24 are formed under the substrate 10. Each land electrode 20 and its respective solder ball 24 are electrically coupled. The solder ball 24 may be used as an electrode for installing the semiconductor device on a mother board, or as an electrode for stacking the semiconductor device to another semiconductor device.
FIG. 1B is a cross-sectional view illustrating semiconductor devices stacked using the package-on-package process. In FIG. 1B, an upper semiconductor device 26 is stacked above a lower semiconductor device 28 using the solder balls 24. The packaging process illustrated in FIG. 1B requires extra real estate to form those solder balls 24 located at the periphery of the resin molding portion 18. In addition, the substrate 10 needs to be stretched to accommodate the solder balls 24 at the periphery, thus adding to the manufacturing cost and complicating the manufacturing process as a result.